
Pulse processing and Analyses
Dušan Kollár,
DNP, FMFI UK
Bratislava



Amplitude (Pulse
Height) Measurements 

Frequency and time response of
amplifiers 

^{Application examples of operational
amplifiers} 

^{Transmission lines} 

Detector equivalent circuits 

Nuclear detector analog signal
processing 

^{Preamplifier} 

^{Linear shapeamplifier} 

ADC  digitization of pulse high 

^{ DAC techniques} 

^{ ADC techniques} 

Timing measurement 

^{ Fast time pickoff signal from input pulse} 

^{ Coincidence system} 

Time interval
measurement 

Digitization of pulse high 
Ideal ADC:
Fig. m51 

Measurement accurancy:
 If all counts of a peak fall in one
channel, then the resolution is DV.
 If the counts are distributed over
sevrel ( >4 or 5) channels, peak fitting can yield a resolution of 10^{1}….10^{2}DV.

Important parameters:
 Resolution;
 Differential nonlinearity ;
 Integral nonlinearity;
 Other common errors (offset, scale
error, nonmonotonicity;
 Conversion time;
Stability;

Resolution 
Simplistic assumption: resolution
defined by number of output bits; e.g. 13 bits => DV/V=1/8192=1,2.10^{4}.
True measure: channel profile
Plot probability vs. pulse amplitude that a
pulse height corresponding to a specific channel is actually converted
to that address.
Diggital conversion errors:

Differential non linerity  DNL 
DNL is measure of equality of channel widths over the range
of the ADC. DNL is computed as max. deviation DV_{i}of the counts in any of the channels from
the average counts<DV>in all channels, expressed as the percentage of the
average counts
DNL = max {(DV_{i}/<DV>)1}
for all channels.
Typically DNL for a 100MHz
Wilkinson ADC: <+ 1% max.
Note: A good instrumentation ADC
specified with an accuracy of + 1LSB may have DNL = 20% to 50%.

Integral nonlinerity INL 
INL  deviation of recorded amplitude from
input amplitude.
Typically values for modern ADC's:
0,01 to 0,1% (~ 1 10 channels for 8k). Today SW correction commonly
used.

Other common errors 
Next figures illustring the definitions of
common digital conversions errors (offset, scale error, nonmonotonicity

Fig. m52
 ADC transfer curve  1/2LSB
offset at zero
 Linear  1 LSB possible error
 + 1/2 LSB nonlinearty (implies
1LSB possible error);
 Nonmonotonic (must be >+1/2
LSB nonlinear).


Count rate performance 
Problem of
spectroscopic resolution generaly due to baseline
shifts with event rate (however, crosswalk from digital to analog
circuitry within ADC can also cause problems). Effect is important when
rate changes during measurement (radioactive decay, beam fluctuations at
accelerators) . So the random rate fluctuation instantaneously leads to
spectral broadening.
Examples
(measurements performed with random
rates): 

Fig. m62
ADC A) inadequate for high
resolution gama ray spectroscopy 
Dead time of the A/D conversion is
the sum of next three times:
 signal acquisition time ( >
time to peak + const)
 conversion time ( > can
depend on pulse hight)
 readout time to memory ( >
usually negligible in MCA`s, but dominant as a rule in multiparameter
computer based systems).

Conversion time 
When detector, preamplifier, spectroscopy
amplifier and ADC are combined to form a spectroscopy system the dead
times of the amplifier and the ADC are in series => extending dead
time. When ( as in illustration fig.)_{.}

Fig. m63
The sources of dead time with
an amplifier and ADC. 
T_{W }

width of
the amplifier pulsemeasuredat the noise discriminators threshold. 
T_{P }

time from
start to point which the ADC detects peak amplitude and
close the linear gate. 
For successive
approximation ADC T_{M} is the fixed conversion time of the ADC
and includes the time required to transfer the data to the subsequent
memory.
For Wilkinson ADC the
value of Dead time (non extending):
T_{M} = (N_{c}/f_{c}) +
T_{MC},
where
f_{c} 

clock
frequency 
T_{MC} 

memory
cycle time 
For f=50  400 MHz, T_{MC}~0,5us 
2us for 8k ADC, T_{M}~20us  165us => long time!!
DNL<1%T
At high counting rates, it is desirable to
have an ADC conversion time that is less then the time taken for the
amplifier pulse to return to the baseline after peak amplitude.

Stability 
Stability vs. temperature + time usually
adequate with modern electronics in laboratory environment (incl. Beam
areas at accelerators). Note that temperature changes within module are
typically much smaller than ambient.
However: highly precise + long term
measurements require spectrum stabilization to compensate for
changes in gain + baseline of overall system.
Technique: using precision pulsers
place a reference peak at low at high end of spectrum:
(peak
position 2)  (peak position 1) 
>
gain, then 
(peak
position 1) or (peak position 2) 
>
offset 
Traditional implementation: hardware,
spectrum stabilizer module today easier to use software to determine
corrections. These can be applied to software calibration or hardware
(simplest and best in ADC circuitry).

DAC  techniques 
DAC  convert a quantity
specified a s binary (or BCD) number to voltage or current proportional
to the value of the digital input. There are a number of popular methods:

Scaled resistors into summing junction 

Fig. m53
Scaled resistor DAC.
Drawback: Height
accuracy chosen bin weighted R!!!

By connecting a set of resistors
to an opamp's summing junction get an
output proportional to a weight sum of the input voltages.

R  2R ladder 
led resistors into summing junction
Set of resistors of two values only.
Switch circuits in realized with transistors

Fig. m54
R2R ladder DAC. 

ADC  techniques 
 Flash ADC ( parallel encoded)
 Successive approximation
 Slope integration (Single /
Dual)

Flash ADC 

Fig.
m55
The principle of flash ADC.
Advantage: short conversion time
Drawback: Limited accuracy
(currently 10bit)
Power consumption
Differential non linearity

Parallel encoder  fastest method of
A/D conversion. The input signal voltage is fed simultaneously to
one input of each n comparators (8 bit requires 256
comparators), the other inputs of which are connected to n  equally
spaced reference voltages. A priority encoder generates a digital
output corresponding to the highest comparator activated by input
voltage. The delay time from input  output equals the sum of
comparator plus encoder delays ( < 20 ns, 10 ns available). Value of
resistors in divider chain ( in IC's) not critical (only matching ).

Single slope ADC 

Fig. m56
The principle of ADC (At the the
beginning of the conversion is the track and hold capacitor C held at
ground.):
 Single slope conversion 
counter is enabled during time T_{conv} . Conversion time depends
on the pulse hight.
 Successive approximation 
for nbit A/D conversion are equired nsteps. Nconversion steps yield 2^{n}
channels, e.g. 8k channels require 13 steps => speed (~us), DNL
(typically 1020%)


Successive approximation ADC 
In successive approximation ADC (according
to fig.) during the rise of the analog input pulse the switch S1 of
linear gate is closed and voltage U_{c1} tracks the rise of the
input signal.

Fig. m57 The basic circuits used with a successive  approximation
ADC. 
When input signal reach maximum amplitude,
linear gate switch S1 is opened, leaving C1 holding the maximum voltage
of the input signal. After detection of the peak amplitude of the input
pulse, the successiveapproximation ADC begins its measurement process.
In this technique you try various
output codes in following turn:
 At the beginning computer
sets all bits initially to 0
 Then each bit in turn,
beginning with MSB, is set provisionally to 1 and the output codes are feeding into DAC and comparing the
result with the analog input via comparator. If
D/A output does not exceed the input signal voltage, the bit is left as
1, otherwise it is set back to 0. For an n  bit A/DC, n such steps are
required.
=> It could be desired as a binary search,
beginning at the middle.
Advantage: speed => fast ( 1ms to 50ms width accuracy 8  12 bits
IC's ( monolithic + hybrid) available.
Drawback: DNL (Typically 10  20%)
(The resistors that set DAC output must be extremely accurately pick and choose. For
DNL < 1% for 12 bit (8k) ADC accuracy < 2,4. 10^{6}

Wilkinson ADC  Dual slope ADC 
Dual slope conversion cycle
consist of:
 capacitor charge time (fixed
) with a current I~U_{in};
 capacitor discharge time (by
a constatnt current, in time Dt_{2}~U_{in} depending on pulse
hight U_{in})

Fig. m58
Dual slope conversion cycle:
t_{1}  capacitor C is fixed
time charged with current I~U_{in}.
t_{2}  capacitor C is
discharged by constant current during time t_{2}~U_{in}.

Signals in Wilkinson ADC
ilustrate next figure.

Fig. m59
Signals in the Wilkinson ADC during
the pulse measurement process.

 The low level discriminator (according
to fig.) is used to recognize the arrival of the pulse => threshold
is set above the noise level to prevent ADC from wasting a lot of time
analyzing noise.
 Output discriminator's pulse opens the
linear gate (LG). => C is connected to input. C is forced to charge
up, so that its U_{c} follows the amplitude of the rising input
pulse.
 When the input pulse has reached its
maximum amplitude and begins to fall LG is closed and C is disconnected
from the input. U_{c} ~ max amplitude of the pulse.
 Following peak amplitude detection a
constant current source is connected to C to cause a linear discharge
(rundown) U_{c}. At the same time, the address clock is
connected to address counter and the clock pulses are counting for the
duration of C discharge.
 When the U_{c} reach zero, the
counting stops. Since the time for linear discharge of C is proportional
to the original pulse amplitude, the number N_{c} recorded in
the address counter is also proportional to the amplitude.
 During the memory cycle the address N_{c}
is located in the memory and +1 count is added to contents of that
location. The value of N_{c }is usually referred as the channel
number.

Fig. m60
Operation of the Wilkinson ADC during
the tree stages of pulse amplitude measurement:
 charging of the rundown capacitor,
 capacitor rundown,
 the memory cycle.


Sliding scale linearization 
The problem of non adequate DNL of
successiveapproximation ADC is solved by adding the sliding scale
linearization (coarse / fine).
After each pulse is analyzed, the 8
bitcounter is incremented. This results in analog voltage being added
to the analog input signal before analysis by the successive
approximation ADC .
If the number in the 8 bit counter is m,
this results in the successive approximation ADC reporting the analysis
mchannels higher then normal. By digitally subtraction on m at the
output of the successive approximation ADC, the digital representation
is brought back to its normal value.
As the 8bit counter increments through its
range after each input pulse, it averages the analysis of each pulse
height over 256 adjacent channels in the successive approximation ADC.
This reduces DNL < 1%.

Fig. m61 The succesive approximation ADC with sliding scale
linearization. 
Advantage: low DNL and short
conversion time independent of the pulse amplitude. Conversion times in
the range from 2  20ms are available with ADC ranging from 1000 to 16 000
channels.

Timing measurements 
 time relationship between 2 events.

Fig. m64
A simple "fastslow"pulse processing
system in which a "slow"amplitude branch is used inly those fast timing
pulses that correspond to events of a predetermined amplitude set by the
SCA window. 


Fig. m65
Example of possible output pulses from
preamplifier:
 fast timing pulse  for timing
puropse;
 Slow pulses shapes  for
amplitude measurement.


Time derivation methods 
Two general types of time derivation
methods called "fast" and "slow" timing are characterized by the ways in
which the signal is derived and by the result obtained.
Fast timing method  unaltered
signals are generated directly at the detectors or signals that have
been shaped specifically for timing.
Slow timing signal are derived from
a linear pulse that has been shaped for optimum energy spectroscopy,
using integrating time constants of the order of 0.25 to 10 ms. They are generated from
the output of spectroscopy amplifier by an instrument such as an
integral discriminator or a timing single channel analyzer. Slow timing
signals are used for coincidence experiments, for gating of linear
energy signals, and for gating a desired range of fasttiming signal.
Fast  slow coincidence.
Accept timing pulse only from events that
are in limited energy range.
Exploit superior energy resolution of slow
channel while retaining fast timing capability of wideband fast channel.
Problem of correct timing
measurements is to obtain a logic signal that is precisely related in
time to event.

Timing measuremnts 
 Time resolution not deterninated by
signaltonoise, but by slopetonoise ratio Dt.


Fig.
m66
Time resolution vs. electronic
noise 
Fig. m67
Optimum trigger level. 
 Increase system bandwidth means:
noise ~ (f_{max})^{0.5}, 
(for white
noise) 
dv/dt ~ 1/t_{r}
~f_{max} 
(but not
beyond dv/dt of signal) 
a) 
Time of
flight (mass of particles, positron measurements in PET, etc); 
b) 
Coincidence
measurements (select events, suppress background); 
a) 
Heavy ion
time of flight: Dt=50ps
FWHM (noise limited); 
b) 
^{60}Co: plastic scintillator  plastic scintillator:^{ }Dt=200ps FWHM (detector
limited); 
c) 
^{60}Co: plastic scintillator  NaI(Tl):^{ }Dt=1ns (detector limited); 
d) 
^{60}Co: plastic scintillator  Ge(Li):^{ }Dt=25ns (detector limited); 

Fasttime pickoff signal from input
pulse 
Methods to
generate fasttime pickoff signal from input pulse
 Leading  Edge
Timing;
 Bipolar pulse and crossover timing;
 Constant  fraction timing;
 Amplitude and Rise  Timing Compensated
Timing.

Leading  Edge Timing 
Drawback: Time of occurrence of
output pulse function of amplitude and rise time => jitter, walk.
Jitter depends on the noise amplitude and the slope of the signal at the
threshold level.


Fig. m68
Leading edge timing. 

Fig. m69
Jitter and walk in leadingedge time
derivation. 
Three important sources of error
can occur in time pickoff measurement:
 Walk 
time movement of the output due to variation in the amplitude of the
input impulse (large volume Ge  variations in shape > dependent
charge transition time.
 Drift  long  term timing error by aging, temp. variation.
 Jitter 
timing uncertainty of pickoff signal influenced by noise in the system
and by statistical fluctuations of the signals from detector.
For example:
 in scintillation / photomultiplier
(PMT) timing systems, jitter is influenced by the variation of
generation rate of photons in the scintillator medium, the transit time
variation of the photoelectrons in the PMT, and the gain variation of
the PMT.
 In silicon charged particle detectors,
jitter is influenced by the leakage current, variations in the detector
capacitance, and preamplifier rise time.

Bipolar pulse and crossover timing 
Method is based on the fact that the
zerocrossing point in a bipolar pulse is very nearly independent on
pulse amplitude, but after amplification with limiting and sequential
shaping walk and jitters yet occurs. Either double delay shaped pulse or
CR shapping may be used, but the former provide better timing
resolution. For purpose zero cross detector a special type of
discriminator is used.


Fig. m70 The principle of zero cross detector:
 Input;
 Amplifier  limiter
 Monovibrator
 Output

This pulse shaping essentially eliminates
amplitude  dependent walk with the uniform rise time.
At the bipolar pulse and crossover timing
method occurrence of the output signal is precisely related to the
occurrence of the detected event and is independent of the "slow" rise
time of the input pulse.

Fig. m71 The principle of bipolar pulse and crossover timing method 

Fig. m72
The bipolar pulse and crossover timing
method is suitable for "slow" scintillator (e.g. NaI(Tl) with flash time
constant T_{s}~0,5ms) in which timing associated on rise pulse time is
problematical.


Fig. m73
Bipolar pulses and crossover timing 
case height and low pulse amplitude. 

Constant  fraction timing (CF
discriminator) 
The input signal (referring to next
figures) is split into 2 parts: One part is attenuated to a fraction f
of the original amplitude and inverted. And the other part of the signal
is delayed .

Fig.
m74a
The principle of constant  fraction
timing (TCF) method. 
(The delay is selected so that the optimum
fraction of the delayed signal occurs at the peak amplitude of the
attenuated signal). Then a zero crossing is detected and used to produce
output logic pulse.
Walk + jitter minimized by proper
adjustment zero  crossing reference selection at attenuating factor +
delay


Fig. m74b
7  input signal
8  attenuated input
9  constant fraction signal
10 zerocrossing time signal

Fig. m74c
Example of various pulse hights.
 t_{r}  rise time of
inverted and attenuated pulse;
 t_{delay}  cable delay.
Result delay of the timing pulse t~t_{delay}
+f t_{r} .


Amplitude and Rise  Timing
Compensated Timing 
Amplitude and Rise  Timing Compensated (ARC)
timing is used when the input signal has a wide range of rise times.
ARC  special case of constantfraction
timing, in which the delay is much shorter. ARC timing can
compensate rise time and amplitude variations of the input signal.

Fig. m75
Signal formation for ARC timing.


Concidence system 
determines if 2 events occurs within a
certain fixed period ( with confidence due to uncertainties associated
with the statistical nature of the process, jitter, walk, drift.


Fig. m76 Coincidence pulses 
Fig. m77 Logical AND example 
Resolving time  period of time t_{r} in which the 2
input pulses can be accepted (the electronic resolving time determined
by the width of 2 pulses).
Coincidence circuits produce logic
output pulses when the input pulses occur within the resolving time
window. Since detector events occur at random times, accidental
coincidences can occur between 2 pulses, which produce background in the
coincidence counting. The rate of random coincidence is given
by

^{(2)}N_{rnd}
= N_{1}*N_{2}*(2t_{r}) 

Where N_{1}
and N_{2} are counting rate in detector 1 and 2 per s; 



or
generally for m input coincidence circuit with resolving time t_{r}: 

^{(m)}N_{rnd}=m*N_{1}*N_{2}*….
N_{m}*(2t_{r})^{(m1)} 
The best way to reduce random
coincidences is to make resolving time as small as possible. However the
resolving time cannot be reduced bellow the amount of time jitter the
detector pulses without losing true coincidence, so the type of
detector determines the minimum resolving time usable.
In order to properly operate the system a
delay curve is obtained in which coincidences are measured as a
function of relative delay between 2 detectors. In ideal case of no time
jitter in either detector a plat region curve is obtained.


Fig. m80b Determination of resolving time  t_{r} = ^{(2)}N_{rnd}/(2*N_{1}*N_{2}*)
based on measurement of random coincidence N_{rnd} number. 
Typical resolving time ~10 ns for energy
range 0,1 to 1 MeV. Shorter resolving time possible for plastic
scintillators, for Sidetectors ~1 ns.

 Fig. m81a Simple true coincidence measurement method. Coincidence
circuit CC_{1} counts n_{1}=n_{c}+n_{rnd}
(number of true n_{c} coincidence and number n_{rnd}
random coincidence). Coincidence circuit CC_{2} counts n_{2}=
n_{rnd} and then number of true coincidence n_{c}= n_{1}n_{2}
can be calculated.
 Fig. m81b Improved true coincidence measurement method.


Fig.
m82 Example of background suppression in
positron annihilation measurement.
Chance coincidence rate: n_{c}=n_{1}n_{2}(Dt_{1}+Dt_{2})~10^{4}
s^{1} (when we suppose that n_{1}=n_{2}=10^{7}s^{1},Dt_{1}=Dt_{2}=1ns). 

Time intervals measuremnts 
– the basic Method for conversion
t>T>D (time t to interval T to digit D).

Fig. m83 The principle of StartStop
Method of time interval measurement. 
B) 
TAC –
the conversion t>A with MCA 
MCA (Multi channel Analysator)
B1) 
Start
– Stop method with integrating capacitor for t>A conversion 

Fig. m84 The principle of startstop time amplitude
(t > A) conversion method. The method is suitable especially
for nanoseconds time intervals, where direct startstop method is hardly
applicable.

B2) 
Coincidence
circuit method with pulse overlap 
and
following integration with capacitor for t>A conversion.

Fig. m85 Time  amplitude (t>A) conversion method
based on input pulses overlap. When T is duration
of the shaped pulse then measured time interval t_{measurement}:

t_{measurement}=
Tt_{overlap} ;

The method is
suitable for fast rise time pulses, which were shaping by delay line
clip.
Advantage: not
dependent on pulse height overlap.

B3) 
TADC –
the conversion t>A>T>D 
(time t to
amplitude A to interval T to digit D conversion). The very short
intervals can be:
 expanded or
 more exactly measured with
interpolation method.
a) Time expander (expands ns
duration intervals to us intervals). Capacitor C_{int} is
quickly charging during measured time interval t_{m }(by great
current –for example 20mA) and after receiving stop pulse is
discharging slowly during time interval T (by low current –for example
80uA). The time expanded by factor T/t_{m} is measured by classic
start  stop method (as in paragraph A). Advantage:
better linearity of conversion then in previously mentioned methods,
while the same capacitor C_{int} is used in both parts of
conversions.

Fig.
m86
The principle of the time
amplitudetime (t>A>t)
conversion. 
b) Nonius (Vernier) method exact interpolation
method
Start pulse
initiates generating pulses at rate T_{1}. After time interval T
(which is point of our interest), the Stop pulse begins generating
pulses at rateT_{2}. (The difference of rates T_{1}T_{2}
is about 1%). When a coincidence after n pulses occurs: T’=nT_{1}=[T_{1}/(T_{1}T_{2})]T=kT.
The
conversion coefficient k=T_{1}/(T_{1}T_{2})
allows to measure (in microsecond) the original nanosecond duration
interval.

Fig.
m87
The principle of the
Nonius method
T  interval, which is
point of our interest
T'  exactly measured
duration, which is proportional to T.


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